High-level synthesis of asynchronous circuits from control data flow graph representations
(translated: Second ACiD-WG Workshop (of the european commission's fifth framework programme), Munich,Germany 28-29 January)
Year: | 2002 |
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(translated: Second ACiD-WG Workshop (of the european commission's fifth framework programme), Munich,Germany 28-29 January)
Year: | 2002 |
---|
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